In the formation of integrated circuits, semiconductor devices are formed on semiconductor substrates, and are then connected through metal layers.
Typically, the formation process of a metal layer includes forming an Inter-Metal Dielectric (IMD), forming trenches and via openings in the IMD, and filling a metallic material in the trenches and via openings to form metal lines and vias, respectively. With the increasing down-scaling of integrated circuits, however, the above-discussed processes experience shortcomings. While the horizontal dimensions (for example, the poly-to-poly pitch between neighboring polysilicon lines) are continuously shrinking, the sizes of the metal lines and vias are reduced. The thickness of the IMD, however, is not reduced accordingly to the same scale as the reduction of the widths of the metal lines and vias. Accordingly, the aspect ratios of the metal lines and vias increase, causing the metal layer formation to be increasingly more difficult.
The down-scaling of integrated circuits results in several problems. First, it is increasingly more difficult to fill the trenches and via openings without causing seam holes (voids) therein. In addition, when the lateral sizes of the metal lines and vias reduce, the sizes of seam holes do not reduce proportionally. This not only causes the effective area of the metal lines and vias for conducting currents to reduce non-proportionally, but also results in the subsequently formed etch stop layers and metal lines to fall into the seam holes, and hence results in reliability problems. As a result, the process window for forming the metal lines and vias becomes narrower and narrower, and the formation of the metal lines and vias has become the bottleneck for the down-scaling of integrated circuits.